1. Field of the Invention
The present invention relates to a semiconductor device such as a BiCMOS device having two or more conductor films used for a wiring portion and an electrode, on its semiconductor substrate, and a method of manufacturing the same.
2. Description of the Related Art
A multi-layer conductive film formed on the main surface of a semiconductor substrate via an interlayer insulation film is used as a wiring portion for electrically connecting an electrode of a semiconductor element, or semiconductor elements with each other. In accordance with a further increase in high integration or further downsizing of semiconductor devices such as IC and LSI, a more fine and complicated pattern is formed on a semiconductor substrate. If, for example, an interlayer insulation film is formed on a surface of a semiconductor substrate on which a fine pattern has been formed, many stepped portions, which result due to the pattern, are formed on the surface. In order to form an electrode or a wiring pattern, made of polysilicon, on an interlayer insulation film on which many stepped portions have been created, a conductive layer made of, for example, polysilicon is formed on the entire surface of an interlayer insulation film, and the conductive layer is etched into a predetermined pattern using an anisotropic etching technique such as RIE, thus forming electrodes and wiring patterns. However, if the anisotropic etching technique such as RIE (reactive ion etching) is used for the conductive layer on such a stepped interlayer insulation film, undesired residue of the conductive layer is likely to result on a side wall portion of a stepped portion while forming a predetermined conductive pattern. Such residue may shortcircuit the integrated circuit and lower the production yield. Conventionally, the following methods are used in order to prevent residue from being created.
i) Removal of residue on side wall of stepped portion by excessive over-etching:
This method may be used without problem if drawback entailed in the method is not created. However, with the downsizing of semiconductor devices, if an underlayer is over-etched, a decrease in the pattern conversion difference is rendered no longer negligible.
ii) Removal of residue on side wall of stepped portion in a different step later:
In this method, the residue is peeled off to be dust in a step prior to the residue removal step, thus lowering the production yield of the semiconductor device. In particular, with reduced-size LSI, a critical decrease in yield may result.
iii) Removal of undesired film formed on stepped portion prior to the anisotropic etching step:
This method is effective in the case where an isotropic etching method capable of selectively and highly controllably removing a film to be removed, from an underlayer. However, in the case where an appropriate isotropic etching method cannot be applied, or where a film to be etched has a laminated structure, which entails a large difference in etching rate while isotropic etching being performed, excessive under-cut occurs, creating the problem of peeling of pattern.
The following is an explanation of a conventional method of producing a BiCMOS device made by the first and second methods, in which the first layer, which is a polysilicon film, is formed into a gate film and the second layer, which is a polysilicon film, is formed into a base lead-out electrode.
First, the first method of removing residue on a side wall by excessive over-etching will now be described with reference to FIGS. 11 to 13.
As shown in FIG. 11, a field oxide film 2 is formed on an element separation region of a silicon semiconductor substrate 1 by an LOCOS method. A gate oxide film 3, which is a heat oxide film made of, for example, silicon, is formed on an element region of a MOS transistor portion on the silicon semiconductor substrate 1. On the gate oxide film 3, a polysilicon gate electrode 4 having a predetermined pattern, which serves as the first conductive film, is formed (FIG. 11). Next, a silicon oxide film (SiO.sub.2) having a thickness of about 100 nm is deposited by the CVD method. Then, the silicon oxide film is etched by a photo-etching method in such a manner that the gate electrode 4 is covered by a photoresist 8, thereby removing the undesired portion of the silicon oxide film. Thus, a silicon oxide film 5 is formed, as shown in FIG. 12. In this figure, the photoresist 8 used for the etching process is formed on the remaining silicon oxide 5. Then, the photoresist 8 is removed.
Next, as shown in FIG. 13, a second layer polysilicon film having a thickness of about 3000 nm, which serves as the second conductive film, is deposited. Then, a photoresist 9 is formed on the second polysilicon film so as to cover a region for forming a base lead-out electrode of a bipolar transistor, in the element region of a bipolar transistor portion. After that, with the photoresist 9 serving as a mask, the polysilicon film is excessively over-etched by an anisotropic etching technique such as RIE, so as to form a base lead-out electrode 6 of the bipolar transistor (FIG. 13). With this method, the following problems arise, that is, (A) a decrease in thickness of the field oxide film 2 and silicon oxide film 5 by over-etching; (B) over-etching of a bipolar portion semiconductor substrate exposed portion; and (C) an increase in the pattern conversion difference of the polysilicon film serving as the second conductive film.
Next, an example of the method of removing only the residue on the side wall of a stepped portion in a different step later will now be described with reference to FIGS. 11, 12, 14 and 15. As shown in FIG. 11, a field oxide film 2 is formed on an element separation region of a silicon semiconductor substrate 1 by an LOCOS method. A gate oxide film 3, which is a heat oxide film made of, for example, silicon, is formed on an element region of a MOS transistor portion on the silicon semiconductor substrate 1. On the gate oxide film 3, a polysilicon gate electrode 4 having a predetermined pattern, which serves as the first conductive film, is formed (FIG. 11). Next, a silicon oxide film (SiO.sub.2) having a thickness of about 100 nm is deposited by the CVD method. Then, the silicon oxide film is etched by a photo-etching method so as to cover the gate electrode 4, thereby removing the undesired portion of the silicon oxide film. Thus, a silicon oxide film 5 is formed, as shown in FIG. 12. In this figure, the photoresist 8 used for the etching process is formed on the remaining silicon oxide film 5. Then, the photoresist 8 is removed. Next, a second layer polysilicon film having a thickness of about 3000 nm, which serves as the second conductive film, is deposited. Then, a photoresist 9 is formed on the second polysilicon film so as to cover a region for forming a base lead-out electrode of a bipolar transistor, in the element region of a bipolar transistor portion.
Then, with the photoresist 9 being used as a mask, the polysilicon film is etched by anisotropic etching such as RIE, thus forming a base lead-out electrode 6 of the bipolar transistor. During this etching, residues 7 of the polysilicon film 6 are formed on the side wall of the stepped portion of the silicon oxide film 5, formed by the gate electrode 4 and the stepped portion of an end of the pattern of the silicon oxide film 5. In a later step, the silicon oxide film 5 is etched, thereby removing the polysilicon film residue. Or, in a later heat process, the polysilicon film residue peels off from the silicon oxide film due to the difference in thermal expansion coefficient between the underlayer and the second conductive film (FIG. 15). In any case, the conventional method of removing residue on the side wall of the polysilicon film serving as the second conductive film, requires much labor to carry out. Thus, it is difficult to handle the residue as dust, which causes deterioration of the quality of the product. The above explanation is made in connection with the case of a polysilicon film; however basically the same explanation can be made in the case of a conductive film of a laminated structure in which the second conductive film consists of a polycide film of a laminated body including a polysilicon film and a titanium silicide formed thereon, and a CVDSiO.sub.2 film applied on the polycide film. In this case, for example, residue which is complicatedly shaped due to a combination of residue pieces of the three films, is formed on the stepped portion of the side wall of a gate electrode.
Further, in the element region of the semiconductor substrate, for example, the gate electrode of the first conductive film formed on the element region on which a MOS transistor is formed, is coated with an insulation film such as the silicon oxide film 5 shown in FIG. 15. This insulation film is not formed in the element region in which a bipolar transistor is formed. That is, the silicon oxide film 5 which is an insulation film, is formed in the element region of the MOS transistor portion, and the silicon oxide film 5 extends onto the field oxide film 2 which is the element separation region. However, the silicon oxide film 5 is exposed to a stress is a heat process later, and a particularly large stress is applied to the end portion of the film. The silicon oxide film 5 may peel off from its end portion during the process of the product or after the completion of the product, thereby causing an increase in the number of defective products. Especially, the residue on the side wall of the polysilicon film is formed also on the peripheral end portion (not shown) of the silicon oxide film 5, and therefore when removing the residue, the silicon oxide film may peel off.
The present invention has been proposed in consideration of the above-described circumstances, and an object thereof is to provide a semiconductor device in which the insulation film covering the conductive film formed on the element region is prevented from being exposed to stress and does not easily peels from its end portion, thus suppressing deterioration of the characteristics, at a high yield rate. Another object thereof is to provide a method of producing a semiconductor device, in which anisotropic etching is carried out so as to avoid formation of side-wall residue, which peels off at a later step and serves as dust.
According to the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a first element region and a second element region; an insulation film formed on the first element region of the semiconductor substrate, having an end portion extending to a region of the semiconductor substrate which is between the first element region and the second element region; a conductive film formed on the end portion, extending onto the insulation film and the semiconductor substrate; and a wiring film formed on the second element region, the wiring film and the conductive film being formed by patterning a common film, and the wiring film and the conductive film being electrically insulated from each other.
According to the present invention, there is further provided a method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having a first element region and a second element region; forming an insulation film on the first element region of the semiconductor substrate, having an end portion extending to a region of the semiconductor substrate which is between the first element region and the second element region; and forming a conductive film on the end portion, extending onto the insulation film and the semiconductor substrate, and a wiring film on the second element region, by patterning a common film.
According to the present invention, there is still further provided a method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having a first element region and a second element region, a projecting film being formed on the first element region of the semiconductor substrate and projected from the first element region; forming an insulation layer over the semiconductor substrate; patterning the insulation layer to form an insulation film covering the projecting film and having an end portion extending to a region of the semiconductor substrate which is between the first element region and the second element region; forming a conductive layer over the semiconductor substrate; forming on the conductive layer, a mask film covering a step portion of the conductive layer which is caused at an edge portion of the projecting film, a mask film covering a step portion of the conductive layer which is caused at the end portion of the insulation film, and a mask film covering a portion of the second element region; patterning the conductive layer by an unisotropic etching, using the mask films, to form a conductive film covering the step portion of the conductive layer which is caused at an edge portion of the projecting film, a conductive film covering the step portion of the conductive layer which is caused at the end portion of the insulation film, and a wiring film covering the portion of the second element region; removing the mask films; forming a mask film on the second element region, covering the wiring layer and the conductive film covering the step portion of the conductive layer which is caused at the end portion of the insulation film; removing the conductive film covering the step portion of the conductive layer which is caused at the edge portion of the projecting film by an isotropic etching, using the mask film; and removing the mask film.
According to the present invention, there is yet further provided a semiconductor device comprising: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate, the semiconductor layer including a MOS transistor region and a bipolar transistor region; a buried layer formed between the semiconductor substrate and the semiconductor layer; an isolation film pattern formed on the semiconductor layer; a source and a drain regions formed in the MOS transistor region of the semiconductor layer; a first conductive film pattern formed in the MOS transistor region of the semiconductor layer, forming a gate electrode; an insulative film pattern formed on the MOS transistor region of the semiconductor layer, covering the first conductive film pattern and having an end portion extending to the isolation film pattern; and a second conductive film pattern having a first conductive portion and a second conductive portion electrically disconnected to each other, the first conductive portion being formed on the bipolar transistor region of the semiconductor layer and the second conductive portion being formed on the isolation film pattern, the first conductive portion forming a base electrode and being connected to a power source potential, and the second conductive portion covering the end portion of the insulative film pattern and being electrically floating.
According to the present invention, there is further provided a semiconductor device comprising: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate, the semiconductor layer including a MOS transistor region and a bipolar transistor region; a buried layer formed between the semiconductor substrate and the semiconductor layer; an isolation film pattern formed on the semiconductor layer; a source and a drain regions formed in the MOS transistor region of the semiconductor layer; a first conductive film pattern formed in the MOS transistor region of the semiconductor layer, forming a gate electrode; a first insulative film pattern formed on the MOS transistor region of the semiconductor layer, covering the first conductive film pattern and having an end portion extending to the isolation film pattern; a second insulative film pattern formed on the MOS transistor region, covering the first insulative film; a second conductive film pattern having a first conductive portion and a second conductive portion electrically disconnected to each other, the first conductive portion being formed on the bipolar transistor region of the second semiconductor layer and the second conductive portion being formed on the isolation film pattern, the first conductive portion forming a base electrode and being connected to a power source potential, and the second conductive portion covering the end portion of the insulative film pattern and being electrically floating; a third conductive film pattern having a third conductive portion and a fourth conductive portion, the third conductive portion and the fourth conductive portion being formed on the first conductive portion and the second conductive portion, covering the first conductive portion and the second conductive portion, respectively; and a third insulative film pattern having a first insulative portion and a second insulative portion, the first insulative portion and the second insulative portion being formed on the third conductive portion and the fourth conductive portion, covering the third conductive portion and the fourth conductive portion, respectively.
According to the provided invention, there is still further provided a method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor layer formed on a semiconductor substrate, the semiconductor layer having a first device region, a second device region and an isolation film pattern between the first and the second device regions; forming a first conductive film pattern on the first device region; forming an insulative film pattern on the first conductive film pattern, the insulative film pattern having an end portion extending to the isolation film pattern; forming a conductive layer over the semiconductor layer; forming first mask film patterns on first portions of the conductive layer which are on the first device region and the edge portion of the isolation film patter; etching second portions of the conductive layer which are other than the first portions, by anisotropic etching using the first mask film patterns; removing the first mask film patterns; forming a second mask film pattern on third portions of the conductive layer which are on the second device portion and the end portion of the insulative film pattern; and etching fourth portions of the conductive layer which are other than the third portions, by isotropic etching using the second mask film patterns.
According to the present invention, there is yet further provided a method of manufacturing semiconductor device, comprising the step of: preparing a semiconductor substrate of a first conductive type; implanting an impurity of a second conductive type into a surface of the semiconductor substrate; growing a semiconductor layer on the semiconductor substrate, for forming a buried layer of the second conductive type by defusing the impurity; boring the semiconductor layer for making a trench reached to the semiconductor substrate; oxidizing a surface of the semiconductor layer including at least an opening of trench, for shaping a field oxide, the field oxide dividing the surface of the semiconductor layer, for building up a first device region and a second device region in the surface of the semiconductor layer, and the second device region being formed upon the buried layer; implanting an impurity of the first conductivity type into the first device region; implanting an impurity into a surface of the first device region, for forming a source region and a drain region; oxidizing the surface of the first device region, for forming a gate insulation film; processing a gate electrode on the gate insulation film; implanting an impurity in the second device region, for constituting a collector region; implanting an impurity in the second device region, for constituting a base region; implanting an impurity in the second device region, for constituting an emitter region; forming an insulative film pattern on the gate electrode, the insulative film pattern having an end portion extending to the field oxide; forming a conductive layer over the semiconductor layer; forming first mask film patterns on first portions of the conductive layer which are upon the first device region, the edge portion of the insulation film, the base region, and emitter region; etching second portions of the conductive layer which are other than the first portions, by anisotropic etching using the first mask film patterns; removing a said first mask film patterns; forming second mask film pattern on third portions of the conductive layer which are on the second device region and the end portion of the insulation film; and etching forth portions of the conductive layer which are other than the third portions, by isotropic etching using the second mask film pattern.
The end portion of the insulation film is coated and protected by the conductive film obtained by patterning the conductive layer, and therefore the insulation film is prevented from being exposed to stress and does not easily peels from the semiconductor substrate. Moreover, since the protection film extends onto the insulation film and the semiconductor substrate, the protection film does not peels off from the films so that the conventional dust problem does not occur. Further, when patterning the conductive layer, the pattern is formed so that the stepped portion formed on the insulation film and the end portion of the insulation film are covered and anisotropic etching is carried out. Thus, the formation of the side-wall residue of the conductive film is avoided. Then, in a later step, the pattern of the conductive film which covers the stepped portion is removed by etching.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.